Senior Designer, IC Layout

SUMMARY:

The Senior IC Layout Designer is mainly responsible for creating section-level layouts. He/she will mostly work with schematic designers, block layout resources, and lead layout people. His/her job is to meet project stakeholders schedule, design, and quality requirements. Depending on the project size, he/she will be handling several block layout resources and it will be his/her task to allocate tasks, set schedules, and provide direction. He/she will have the opportunity to mentor new hires or interns and may likewise be tapped to be a part of other development initiatives for the layout team.

KEY QUALIFICATIONS:

• Extensive section (multi-hierarchical) level layout experience
• Top/Chip level layout is an advantage
• Strong fundamental knowledge in semiconductor device physics, cross-section, and construction
• Strong fundamental knowledge of layout principles, IC reliability, and failure mechanisms
• Proficiency in Cadence Virtuoso XL and Calibre verification tools is an advantage

EDUCATION & EXPERIENCE:

• BS Electronics or Electrical Engineering
• At least 4 years of relevant working experience

ADDITIONAL REQUIREMENTS:

• Strong communication skills, both oral and written
• Able to work and effectively collaborate with a cross-functional and global team
• Strong leadership skills
• Layout experience in any of the following areas is an advantage: ADC, DAC, High-voltage applications
• Layout experience in the following technology nodes is a plus: 0.18um, 40nm